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| mos integrated circuit m pd17215, 17216, 17217, 17218 description m pd17215, 17216, 17217, 17218 (hereafter called m pd17215 subseries) are 4-bit single-chip microcontrollers for small general-purpose infrared remote control transmitters. it employs a 17k architecture of general-purpose register type devices for the cpu, and can directly execute operations between memories instead of the conventional method of executing operations through the accumulator. moreover, all the instructions are 16-bit 1-word instructions which can be programmed efficiently. in addition, a one-time prom model, m pd17p218, to which data can be written only once, is also available. it is convenient either for evaluating the m pd17215 subseries programs or small-scale production of application systems. detailed functions are described in the follwing manual. be sure to read this manual when designing your system. m pd172 subseries user's manual: ieu-1317 features ? infrared remote controller carrier generator circuit (rem output) ? 17k architecture: general-purpose register system ? program memory (rom), data memory (ram) m pd17215 m pd17216 m pd17217 m pD17218 program memory (rom) 4 k bytes 8 k bytes 12 k bytes 16 k bytes (2048 16) (4096 16) (6144 16) (8192 16) data memory (ram) 111 4 bits 223 4 bits ? 8-bit timer : 1 channel ? basic internal timer / watchdog timer: 1 channel (wdout output) ? instruction execution time (can be changed in two steps) at f x 4 mhz : 4 m s (high-speed mode)/8 m s (ordinary mode) at f x 8 mhz : 2 m s (high-speed mode)/4 m s (ordinary mode) ? external interrupt pin (int) : 1 ? i/o pins : 20 ? supply voltage : v dd = 2.2 to 5.5 v (at f x = 4 mhz (high-speed mode)) v dd = 2.0 to 5.5 v (at f x = 4 mhz (ordinary mode)) ? low-voltage detector circuit (mask opation) unless otherwise specified, the m pd17215 is treated as the representative model throughout this document. the mark shows major revised points. document no. u12042ej3v0ds00 (3rd edition) (previous no. icC3249) date published january 1997 n printed in japan 1993 data sheet the information in this document is subject to change without notice. 4-bit single-chip microcontroller for small general-purpose infrared remote control transmitter
m pd17215, 17216, 17217, 17218 2 application preset remote controllers, toys, portable systems, etc. ordering information part number package m pd17215ct-xxx 28-pin plastic shrink dip (400 mil) m pd17215gt-xxx 28-pin plastic sop (375 mil) m pd17216ct-xxx 28-pin plastic shrink dip (400 mil) m pd17216gt-xxx 28-pin plastic sop (375 mil) m pd17217ct-xxx 28-pin plastic shrink dip (400 mil) m pd17217gt-xxx 28-pin plastic sop (375 mil) m pD17218ct-xxx 28-pin plastic shrink dip (400 mil) m pD17218gt-xxx 28-pin plastic sop (375 mil) remark: xxx is rom code number. m pd17215, 17216, 17217, 17218 3 pin configuration (top view) ? 28-pin plastic sop (375 mil) m pd17215gt-xxx, 17216gt-xxx, 17217gt-xxx, 17218gt-xxx ? 28-pin plastic shrink dip (400 mil) m pd17215ct-xxx, 17216ct-xxx, 17217ct-xxx, 17218ct-xxx p0d 2 p0d 3 int p0e 0 p0e 1 p0e 2 p0e 3 rem v dd x out x in gnd reset wdout p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd : ground int : external interrupt request signal input p0a 0 -p0a 3 : input port (cmos input) p0b 0 -p0b 3 : input port (cmos input) p0c 0 -p0c 3 : output port (n-ch open-drain output) p0d 0 -p0d 3 : output port (n-ch open-drain output) p0e 0 -p0e 3 : i/o port (cmos push-pull output) rem : remote controller output (cmos push-pull output) reset : reset input v dd : power supply wdout : hang-up/low voltage detection output (n-ch open-drain output) x in , x out : oscillator connection m pd17215, 17216, 17217, 17218 4 block diagram p0a 0 p0a 1 p0a 2 p0a 3 p0b 0 p0c 0 p0d 0 p0e 0 p0b 1 p0c 1 p0d 1 p0e 1 p0b 2 p0c 2 p0d 2 p0e 2 p0b 3 p0c 3 p0d 3 p0e 3 p0a p0b p0c p0d p0e rf system reg. alu remote control divider rem int 8-bit timer interrupt controller reset wdout v dd gnd x in x out instruction decoder program counter stack (5 levels) basic interval/ watchdog timer power supply circuit cpu clock osc pd17215, 17216 : 111 4 bits pd17217, 17218 : 223 4 bits m rom pd17215 : 2048 16 bits pd17216 : 4096 16 bits pd17217 : 6144 16 bits pD17218 : 8192 16 bits rom m m m m m m pd17215, 17216, 17217, 17218 5 contents 1. pin functions ................................................................................................................ .............. 7 1.1 pin function list ........................................................................................................... .......................... 7 1.2 input/output circuits ....................................................................................................... ........................ 8 1.3 processing of unused pins ................................................................................................... .................. 9 1.4 notes on using int and reset pins ........................................................................................... .......... 9 2. memory space ................................................................................................................. ............ 10 2.1 program counter (pc) ........................................................................................................ .................... 10 2.2 program memory (rom) ........................................................................................................ ................ 10 2.3 stack ....................................................................................................................... ................................ 12 2.4 data memory (ram) ........................................................................................................... .................... 14 2.5 register file (rf) .......................................................................................................... ......................... 21 3. ports ........................................................................................................................ ...................... 24 3.1 port 0a (p0a 0 -p0a 3 ) .............................................................................................................................. .24 3.2 port 0b (p0b 0 -p0b 3 ) .............................................................................................................................. .24 3.3 port 0c (p0c 0 -p0c 3 ) .............................................................................................................................. 24 3.4 port 0d (p0d 0 -p0d 3 ) .............................................................................................................................. 24 3.5 port 0e (p0e 0 -p0e 3 ) .............................................................................................................................. .24 3.6 int pin ..................................................................................................................... ............................... 25 3.7 switching bit i/o ........................................................................................................... .......................... 26 3.8 specifying pull-up sesistor connection ...................................................................................... ............. 27 4. clock generator circuit ...................................................................................................... 28 4.1 instruction execution time (cpu clock) selection ............................................................................ ..... 28 5. 8-bit timer and remote controller carrier generator circuit ........................ 29 5.1 configuration of 8-bit timer (with modulo function) ......................................................................... ........ 29 5.2 function of 8-bit timer (with modulo function) .............................................................................. .......... 31 5.3 carrier generator circuit for remote controller ............................................................................. ......... 32 6. basic interval timer/watchdog timer ............................................................................. 36 6.1 source clock for basic interval timer ....................................................................................... .............. 36 6.2 controlling basic interval timer ............................................................................................ .................. 36 6.3 operation timing for watchdog timer ......................................................................................... ........... 38 7. interrupt functions .......................................................................................................... ...... 39 7.1 interrupt sources ........................................................................................................... ......................... 39 7.2 hardware of interrupt control circuit ....................................................................................... ............... 40 7.3 interrupt sequence .......................................................................................................... ....................... 44 m pd17215, 17216, 17217, 17218 6 8. standby functions ............................................................................................................ ....... 46 8.1 halt mode ................................................................................................................... .......................... 46 8.2 halt instruction execution conditions ....................................................................................... ............ 47 8.3 stop mode ................................................................................................................... ......................... 47 8.4 stop instruction execution conditions ....................................................................................... ............ 49 8.5 releasing standby mode ...................................................................................................... .................. 49 9. reset ........................................................................................................................ ...................... 50 9.1 reset by reset signal input ................................................................................................. .................. 50 9.2 reset by watchdog timer (connect reset and wdout pins) ............................................................ 50 9.3 reset by stack pointer (connect reset and wdout pins) ................................................................. 51 10. low-voltage detector circuit (connect reset and wdout pins) ....................... 51 11. assembler reserved words ................................................................................................ 52 11.1 mask option directives ..................................................................................................... ...................... 52 11.2 reserved symbols ........................................................................................................... ....................... 53 12. instruction set ............................................................................................................. ............. 58 12.1 instruction set outline .................................................................................................... ........................ 58 12.2 legend ..................................................................................................................... ............................... 59 12.3 list of instruction sets ................................................................................................... ......................... 60 12.4 assembler (as17k) built-in macro instruction ............................................................................... ......... 62 13. electrical specifications ................................................................................................... .63 14. characteristic waveforms (reference value) ........................................................... 70 15. application circuit example ................................................................................................ 7 3 16. package drawings ............................................................................................................ ....... 74 17. recommended soldering conditions ............................................................................... 76 appendix a. differences among m pd17215, 17216, 17217, 17218 and m pd17p218 ............ 77 appendix b. functional comparison of m pd17215 subseries related products ...... 78 appendix c. development tools ............................................................................................... 79 m pd17215, 17216, 17217, 17218 7 1. pin functions 1.1 pin function list no. symbol function output form on reset 15 p0a 0 16 p0a 1 17 p0a 2 18 p0a 3 19 p0b 0 20 p0b 1 21 p0b 2 22 p0b 3 23 p0c 0 24 p0c 1 25 p0c 2 26 p0c 3 27 p0d 0 28 p0d 1 1 p0d 2 2 p0d 3 4 p0e 0 5 p0e 1 6 p0e 2 7 p0e 3 8 rem 13 reset 9v dd power supply 12 gnd ground 3 int external interrupt request signal input 14 wdout 11 x in connects ceramic oscillator for system clock oscillation 10 x out 4-bit cmos input port with pull-up resistor. can be used for key return input of key matrix. when at least one of these pins goes low, standby function is released. 4-bit input/output port. can be set in inputset in input or output mode in 1-bit units. in output mode, this port functions as a highcurrent cmos output port. in input mode, function as cmos input and can bespecified to connect pull-up resistor by program. 4-bit n-ch open-drain output port. can be used for key source output of key matrix. 4-bit cmos input port with pull-up resistor. can be used for key return input of key matrix. when at least one of these pins goes low,standby function is released. 4-bit n-ch open-drain output port. can be used for key source output of key matrix. - input - input system reset input. cpu can be reset when low-level signal is input to this pin. while low-level signal is input, oscillator circuit is stopped. can be connected to pull-upresistor by mask option. output detecting hang-up and drop in supply voltage.this pin outputs at low level either when an overflow occurs in the watchdog timer, when an overflow/underflow occurs in the stack, or when the supply voltage drops below a specified level (mask option). connect this pin to the reset pin. - input -- -- - input outputs transfer signal for infrared remotecontroller. active-high output. n-ch low- open- level drain output n-ch low- open- level drain output cmos low-level pusl-pll output - (oscillation stops) cmos push- input pull high- impedance low-level output at low voltage detection n-ch open- drain ? ? ? ? ? ? ? ? ? ? m pd17215, 17216, 17217, 17218 8 1.2 input/output circuits the equivalent input/output circuit for each m pd17215 pin is shown below. (1) p0a, p0b v dd input buffer (2) p0c, p0d output latch data n-ch (3) p0e v dd data data p-ch p-ch n-ch v dd input buffer output disable pull-up register output latch selector (4) reset v dd input buffer mask option schmitt trigger input with hysteresis charac- teristics (5) int input buffer schmitt trigger input with hysteresis characteristics (6) rem data p-ch n-ch v dd output disable (7) wdout data n-ch m pd17215, 17216, 17217, 17218 9 1.3 processing of unused pins process the unused pins as follows: table 1-1 processing of unused pins pin recommended connection p0a 0 -p0a 3 connect to v dd p0b 0 -p0b 3 connect to v dd p0c 0 -p0c 3 connect to gnd p0d 0 -p0d 3 connect to gnd p0e 0 -p0e 3 input : connect to v dd or gnd output : open rem open int connect to gnd wdout connect to gnd 1.4 notes on using int and reset pins in addition to the functions shown in 1.1 pin functions, the int and reset pins also have a function to set a test mode (for ic testing) in which the internal operations of the m pd17215 are tested. when a voltage higher than v dd is applied to either of these pins, the test mode is set. this means that, even during ordinary operation, the m pd17215 may be set in the test mode if a noise exceeding v dd is applied. for example, if the wiring length of the int or reset pin is too long, noise superimposed on the wiring line of the pin main cause the above problem. therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. ? connect diode with low v f between v dd and int/reset pin v dd v dd v dd v dd int, reset int, reset diode with low v f if the test mode is set by the int pin, low level is output from the wdout pin. in this case, connect the wdout and reset pin. ? connect capacitor between v dd and int/reset pin m pd17215, 17216, 17217, 17218 10 2. memory space 2.1 program counter (pc) the program counter (pc) specifies an address of the program memory (rom). the program counter is a 11/12/13-bit binary counter as shown in fig. 2-1. its contents are initialized to address 0000h at reset. fig. 2-1 configuration of program counter msb page pc12 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 lsb pc11 pc ( pd17215) pc ( pd17216) pc ( pd17217, 17218) m m m 2.2 program memory (rom) the configuration of the program memory is as follows: part number capacity address m pd17215 2048 x 16 bits 0000h-07ffh m pd17216 4096 x 16 bits 0000h-0fffh m pd17217 6144 x 16 bits 0000h-17ffh m pD17218 8192 x 16 bits 0000h-1fffh the program memory stores a program, interrupt vector table, and fixed data table. the program memory is addressed by the program counter. fig. 2-2 shows the program memory map. the entire range of the program memory can be addressed by the bd addr, br @ar, call @ar, movt dbf, and @ar instructions. note, however, that the subroutine entry addresses that can be specified by the call addr instruction are from 0000h to 07ffh. m pd17215, 17216, 17217, 17218 11 fig. 2-2 program memory map address 0 0 0 0 h 0 0 0 1 h 0 0 0 2 h 0 0 0 3 h 0 f f f h 1 7 f f h 1 f f f h 16 bits reset start address basic interval timer interrupt vector external input (int) interrupt vector 8-bit timer interrupt vtor ( pd17217) page 0 page 1 subroutine entry addresses for call addr instruction branch addresses for br addr instruction branch addresses for br @ar instruction subroutine entry addresses for call @ar instruction table reference addresses for movt dbr, @ar instruction ( pD17218) page 2 page 3 0 7 f f h ( pd17215) ( pd17216) m m m m m pd17215, 17216, 17217, 17218 12 2.3 stack a stack is a register to save a program return address and the contents of system registers (to be described later) when a subroutine is called or when an interrupt is accepted. 2.3.1 stack configuration fig. 2-3 shows the stack configurarion. a stack consists of a stack pointer (a 4-bit binary counter, the upper 1-bit fixed to 0), five 11-bit ( m pd17215)/12-bit ( m pd17216)/13-bit ( m pd17217, 17218) address stack registers, and three 5-bit ( m pd17215, 17216)/6-bit ( m pd17217, 17218) interrupt stack registers. fig. 2-3 stack configuration address stack registers (asr) b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address stack register 1 address stack register 2 address stack register 3 address stack register 4 b 2 b 1 b 0 spb 2 spb 1 spb 0 stack pointer (sp) 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h interrupt stack registers (intsk) banksk1 banksk2 bcdsk0 bcdsk1 bcdsk2 cmpsk0 cmpsk1 cmpsk2 cysk0 cysk1 cysk2 zsk0 zsk1 zsk2 ixesk0 ixesk1 ixesk2 address stack register 0 wdout pin goes low when the contents of the stack pinter are 6h-7h. b 3 0 b 12 pd17215 pd17216 pd17217, 17218 b 4 b 3 b 2 b 5 banksk0 b 1 b 0 m m m undefined undefined undefined pd17215, 17216 pd17217, 17218 m m m pd17215, 17216, 17217, 17218 13 2.3.2 function of stack the address stack register stores a return address when the subroutine call instruction or table reference instruction (first instruction cycle) is executed or when an interrupt is accepted. it also stores the contents of the address registers (ars) when a stack manipulation instruction (push ar) is executed. the wdout pin goes low if a subroutine call or interrupt exceeding 5 levels is executed. the interrupt stack register (intsk) saves the contents of the bank register (bank) and program status word (psword) when an interrupt is accepted. the saved contents are restored when an interrupt return (reti) instruction is executed. intsk saves data each time an interrupt is accepted, but the data stored first is lost if more than 3 levels of interrupts occur . 2.3.3 stack pointer (sp) and interrupt stack pointer table 2-1 shows the operations of the stack pointer (sp). the stack pointer can take eight values, 0h-07. because there are only five stack registers available, however, the wdout pin goes low if the value of sp is 6 or greater . table 2-1 operations of stack pointer instruction value of stack pointer (sp) counter of interrupt stack register call addr call @ar movt dbf, @ar C1 0 (1st instruction cycle) push ar when interrupt is accepted C1 C1 ret retsk movt dbf, @ar +1 0 (2nd instruction cycle) pop ar ret1 +1 +1 m pd17215, 17216, 17217, 17218 14 2.4 data memory (ram) data memory (random access memory) stores data for operations and control. it can be read-/write-accessed by instructions. 2.4.1 memory configuration figure 2-4 shows the configuration of the data memory (ram). the data memory consists of two banks: bank0 and bank1. in each bank, every 4 bits of data is assigned an address. the higher 3 bits of the address indicate a row address and the lower 4 bits of the address indicate a column address. for example, a data memory location indicated by row address 1h and column address 0ah is termed a data memory location at address 1ah. each address stores data of 4 bits (= a nibble). in addition, the data memory is divided into following six functional blocks: (1) system register (sysreg) a system register (sysreg) is resident on addresses 74h to 7fh (12 nibbles long) of each bank. in other nibbles, each bank has a system register at its addresses 74h to 7fh. (2) data buffer (dbf) a data buffer is resident on addresses 0ch to 0fh (4 nibbles long) of bank 0 of data memory. the reset value is 0320h. (3) general register (gr) a general register is resident on any row (16 nibbles long) of any bank of data memory. the row address of the general register is pointed by the general pointer (rp) in the system register (sysreg). (4) port register a port data register is resident on addresses 6fh, and 70h to 73h (5 nibbles) of bank0 of data memory. no data can be written to the addresses 70h to 73h of bank1 (the values of addresses 70h to 73h of bank0 are read in this case). m pd17215 and 17216 are not provided with bank1. m pd17215, 17216, 17217, 17218 15 (5) general-purpose data memory the general-purpose data memory area is an area of the data memory excluding the system register area, and the port register area. this memory area has a total of 223 nibbles (111 nibbles in bank0 and 112 nibbles in bank1). m pd17215 and 17216 are not provided with bank1. fig. 2-4 configuration of data memory 0123456789abcdef 0 1 2 3 4 5 6 7 bank 0 0123456789abcdef bank 1 system register (sysreg) example : address 1ah in bank 0 system register (sysreg) row address row address column address data buffer (dbf) p0a p0b p0c p0d p0e column address caution: no data can be written to the addresses 70h to 73h of bank1 (the value of p0a to p0d are read in this case). m pd17215, 17216, 17217, 17218 16 2.4.2 system registers (sysreg) the system registers are registers that are directly related to control of the cpu. these registers are mapped to addresses 74h-7fh on the data memory and can be referenced regardless of bank specification. the system registers include the following registers: address registers (ar0-ar3)* window register (wr) bank register (bank)* memory pointer enable flag (mpe) memory pointers (mph, mpl) index registers (ixh, ixm, ixl) general register pointers (rph, rpl) program status word (psword) *: the address register (ar3) and the bank register (bank) are fixed to 0 in the m pd17215 and 17216. fig. 2-5 configuration of system register b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh ar 3 ar 2 ar 1 ar 0 wr bank ixh ixm ixl rph rpl psw mph mpl address register (ar) window register (wr) bank register (bank) data memory row address pointer (mp) index register (ix) general register pointer (rp) program status word (psword) 000 00 00 00 m p e b c d c m p c yz i x e (rp) (ix) (mp) (bank) data bit symbol name address initial value at reset 0000000000000000 0000000000000000000000000000 undefined 0 0 0 (wr) * * * * (ar) ( pd17217, 17218) (ar) ( pd17216) (ar) ( pd17215) m 00000 0000 m m *: this bit is fixed to 0 in the m pd17215 and 17216. m pd17215, 17216, 17217, 17218 17 2.4.3 general register (gr) a general register is a 16-word register on the data memory and used for arithmetic operations and transfer of data to and from the data memory. (1) configuration of general register figure 2-6 shows the configuration of the general register. a general register occupies 16 nibbles (16 x 4 bits) on a selected row address of the data memory. the row address is selected by the general register pointer (rp) of the system register. the rp having four significant bits in the m pd17217 and 17218 can point to any row address in the range of 0h to 7h of each bank (bank0 and bank1). in the m pd17215 and 17216, 3 bits are available in the rp. these bits can point to any row address in the range of 0h to 7h of bank0. (2) functions of the general register the general register enables an arithmetic operation and data transfer between the data memory and a selected general register by a single instruction. as a general register is a part of the data memory, you can say that the general register enables arithmetic operation and data transfer between two locations of the data memory. similarly, the general register can be accessed by a data memory manipulation instruction as it is a part of the data memory. fig. 2-6 configuration of general registers (rp) rph rpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 0 1001 1 1010 2 1011 3 1100 4 1101 5 1110 6 1111 7 0123456789abcdef rp system registers port register general registers (16 nibbles) general register pointer bank0 bank1 column address general register settable range f i x e d t o 0 a s s i g n e d t o b c d f l a g ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? system registers example: general registers when rp = 0000010b same system registers exist f i x e d t o 0 f i x e d t o 0 port regis- ter m pd17215, 17216, 17217, 17218 18 2.4.4 data buffer (dbf) the data buffer on the addresses 0ch to 0fh of data memory is used for data transfer to and from peripheral hardware and for storage of data during table reference. (1) functions of the data buffer the data buffer has two major functions: a function to transfer to and from hardware and a function to read constant data from the program memory (for table reference). figure 2-7 shows the relationship between the data buffer and peripheral hardware. fig. 2-7 data buffer and peripheral hardware data buffer (dbf) internal bus program memory (rom) constant data peripheral address peripheral hardware 8-bit timer (tmc, tmm) carrier generator for remote controller (nrzltmm, nrzhtmm) address register (ar) 05h, 06h 03h, 04h 40h m pd17215, 17216, 17217, 17218 19 table 2-2 relations between hardware peripherals and data buffer peripheral register transferring data with data buffer hardware peripherals name symbol peripheral data put/get address buffer 8-bit counter tmc 05h dbf0, dbf1 get only 8-bit timer 8-bit modulo tmm 06h dbf0, dbf1 put only register nrz low put level period get setting nrzltmm 03h dbf0, dbf1 remote modulo controller register carrier generator nrz high put (clear bit 3 level period of dbf1 to 0) setting nrzhtmm 04h dbf0, dbf1 get (bits 3 of modulo dbf1 is always 0) register put (bits 0 to 3 of ar3 and bit 3 of address address ar 40h dbf0-dbf3 ar2 are any) * 1 register register get (bits 0 to 3 of ar3 and bit 3 of ar2 are always 0) * 2 *1: in the m pd17216: bits 0 to 3 of ar3 are any, in the m pd17217, 17218: bits 1 to 3 of ar3 are any 2: in the m pd17216: bits 0 to 3 of ar3 are always 0, in the m pd17217, 17218: bits 1 to 3 of ar3 are always 0 (2) table reference a movt instruction reads constant data from a specified location of the program memory (rom) and sets it in the data buffer. the function of the movt instruction is explained below. movt dbf,@ar: reads data from a program memory location pointed to by the address register (ar) and sets it in the data buffer (dbf). dbf 3 dbf 2 dbf 1 dbf 0 movt dbf, @ ar b 15 b 0 16 bits program memory (rom) data buffer m pd17215, 17216, 17217, 17218 20 (3) note on using data buffer when transferring data to/from the peripheral hardware via the data buffer, the unused peripheral addresses, write-only peripheral registers (only when executing put), and read-only peripheral registers (only when executing get) must be handled as follows: ? when device operates nothing changes even if data is written to the read-only register. if the unused address is read, an undefined value is read. nothing changes even if data is written to that address. ? using assembler an error occurs if an instruction is executed to read a write-only register. again, an error occurs if an instruction is executed to write data to a read-only register. an error also occurs if an instruction is executed to read or write an unused address. ? if an in-circuit emulator (ie-17k or ie-17k-et) is used (when instruction is executed for patch processing) an undefined value is read if an attempt is made to read the data of a write-only register, but an error does not occur. nothing changes even if data is written to a read-only register, and an error does not occur. an undefined value is read if an unused address is read; nothing changes even if data is written to this address. an error does not occur. m pd17215, 17216, 17217, 17218 21 2.5 register file (rf) the register file mainly consists of registers that set the conditions of the peripheral hardware. these registers can be controlled by dedicated instructions peek and poke, and the embedded macro instructions of as17k, setn, clrn, and initflg. 2.5.1 configuration of register file fig. 2-8 shows the configuration of the register file and how the register file is accessed by the peek and poke instructions. the control registers are controlled by using dedicated instructions peek and poke. since the control registers are assigned to addresses 00h-3fh regardless of the bank, the addresses 00h-3fh of the general-purpose data memory cannot be accessed when the peek or poke instruction is used. the addresses that can be accessed by the peek and poke instructions are the addresses 00h-3fh of the control registers and 40h-7fh of the general-purpose data memory. the register file consists of these addresses. the control registers are assigned to addresses 80h-bfh on the ie-17k to facilitate debugging. fig. 2-8 register file access with peek or poke instructions 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address data memory system register 0 1 2 3 peek wr, sp poke lcdmd, wr poke m063, wr control register register file m pd17215, 17216, 17217, 17218 22 2.5.2 control registers the control registers consists of a total of 64 nibbles (64 x 4 bits) of the addresses 00h-3fh of the register file. of these, however, only 14 nibbles are actually used. the remaining 50 nibbles are unused registers that are inhibited from being read or written. when the peek wr, rf instruction is executed, the contents of the register file addressed by rf are read to the window register. when the poke rf, wr instruction is executed, the contents of the window register are written to the register file addressed by rf. when using the assembler (as17k), the macro instructions listed below, which are embedded as flag type symbol manipulation instructions, can be used. the macro instructions allow the contents of the register file to be manipulated in bit units. for the configuration of the control register, refer to fig. 11-1 register file list. setn : sets flag to 1 clrn : sets flag to 0 sktn : skips if all flags are 1 skfn : skips if all flags are 0 notn : complements flag initflg: initializes flag 2.5.3 notes on using register files when using the register files, bear in mind the points described below. for details, refer to m pd172xx subseries users manual (ieu-1317) . (1) when manipulating control registers (read-only and unused registers) when manipulating the write-only (w), the read-only (r) and unused control registers by using the assembler or in-circuit emulator, keep in mind the following points: ? when device operates nothing changes even if data is written to the read-only register. if the unused register is read, an undefined value is read; nothing is changed even if data is written to this register. ? using assembler an error occurs if instruction is excecuted to read data to the write-only register. an error occurs if an instruction is executed to write data to the read-only register. an error also occurs if an instruction is executed to read or write the unused address. ? when an in-circuit emulator (ie-17k or ie-17k-et) is used (when instruction is executed for patch processing) an undefined value is read if the write-only register is read, and an error does not occur. nothing changes even if data is written to the read-only register, and an error does not occur. an undefined value is read if the unused address is read; nothing changes even if data is written to this address. an error does not occur. m pd17215, 17216, 17217, 17218 23 (2) symbol definition of register file an error occurs if a register file address is directly specified as a numeral by the operand rf of the peek wr, rf or poke rf, wr instruction if the 17k series assembler (as17k) is being used. therefore, the addresses of the register file must be defined in advance as symbols. to define the addresses of the control registers as symbols, define them as the addresses 80h-bfh of bank0. the portion of the register file overlapping the data memory (40h-7fh), however, can be defined as symbols as is. m pd17215, 17216, 17217, 17218 24 3. ports 3.1 port 0a (p0a 0 -p0a 3 ) this is a 4-bit input port. data is read through port register p0a (address 70h). this port is a cmos input port with a pull-up resistor, and can be used for key return input for a key matrix. when a low-level signal is input to at least one of the pins in this port in the standby mode, the standby mode is released. 3.2 port 0b (p0b 0 -p0b 3 ) this is a 4-bit input port. data is read through port register p0b (address 71h). this port is a cmos input port with a pull-up resistor, and can be used for key return input for a key matrix. when a low-level signal is input to at least one of the pins in this port in the standby mode, the standby mode is released. 3.3 port 0c (p0c 0 -p0c 3 ) this is a 4-bit output port. the contents of the output latch are read and output data is set through port register p0c (address 72h). this port is an n-ch open-drain output port, and can be used as the key source of a key matrix. in the standby mode, this port outputs low-level signals. 3.4 port 0d (p0d 0 -p0d 3 ) this is a 4-bit output port. the contents of the output latch are read and output data is set through port register p0d (address 73h). this port is an n-ch open-drain output port, and can be used as the key source for a key matrix. in the standby mode, this port outputs low-level signals. 3.5 port 0e (p0e 0 -p0e 3 ) this is a 4-bit i/o port which can be set in either the input or output mode in 1-bit units by the p0ebio (address 27h) of the register file. to read the input data or to set the output data, use the p0e register (address 6f). when data is read in the output mode, the contents of the output latch are read. connection of a pull-up resistor can be specified in 1-bit units by the p0ebpu (address 17h) of the register file. (when the pull-up resistor is connected, note that the pull-up resistor is not disconnected even when the output mode is set.) on reset, this port functions as an input port. m pd17215, 17216, 17217, 17218 25 3.6 int pin this pin inputs an external interrupt request signal. at either the rising or falling edge of the signal input to this pin, th e irq flag (rf: address 3eh, bit 0) is set. the status of this pin can be read by using the int flag (rf: address 0fh, bit 0). when the high level is input to the pin, the int flag is set to 1; when the low level is input, the flag is reset to 0 (refer to 7.2.1 int). fig. 3-1 relations between port register and each pin bank address bit port output form 70h port 0a input only 0 71h port 0b 72h port 0c n-ch open-drain (output only) 73h port 0d b 3 b 2 b 1 b 0 p0a 3 p0a 2 p0a 1 p0a 0 b 3 b 2 b 1 b 0 p0b 3 p0b 2 p0b 1 p0b 0 b 3 b 2 b 1 b 0 p0c 3 p0c 2 p0c 1 p0c 0 b 3 b 2 b 1 b 0 p0d 3 p0d 2 p0d 1 p0d 0 6fh port 0e coms push-pull b 3 b 2 b 1 b 0 p0e 3 p0e 2 p0e 1 p0e 0 contents to be read input mode output mode pin status pin status output latch on reset input mode (w/pull-up resistor) output mode (low level output) input mode (w/pull-up resistor) contents to be written input mode output mode output latch output latch m pd17215, 17216, 17217, 17218 26 3.7 switching bit i/o the i/o which can be set in the input or output mode in bit units is called a bit i/o. p0e is a bit i/o port, which can be set in the input or output mode in bit units by the register file shown below. when the mode is changed from input to output, the p0e output latch contents are output to the port lines, as soon as the mode has been changed. 32 10 p0ebio3 p0ebio2 p0ebio1 p0ebio0 address: rf : 27h p0ebio0 on reset: 0h r/w: r/w 0 1 sets p0e input/output mode sets p0e in input mode sets p0e in output mode p0ebio1 0 1 p0ebio2 0 1 p0ebio3 0 1 0 0 0 sets p0e input/output mode sets p0e in input mode sets p0e in output mode 1 1 1 sets p0e input/output mode sets p0e in input mode sets p0e in output mode 2 2 2 sets p0e input/output mode sets p0e in input mode sets p0e in output mode 3 3 3 m pd17215, 17216, 17217, 17218 27 3.8 specifying pull-up resistor connection whether or not a pull-up resistor is connected to port p0e can be specified by the following registers of the register file in 1-bit units when the port is in the input mode*. 32 10 p0ebpu3 p0ebpu2 p0ebpu1 p0ebpu0 address: rf : 17h p0ebpu0 on reset: 0h r/w: r/w 0 1 connects pull-up resistor to p0e p0ebpu1 0 1 p0ebpu2 0 1 p0ebpu3 0 1 0 not connected connected connects pull-up resistor to p0e 1 not connected connected connects pull-up resistor to p0e 2 not connected connected connects pull-up resistor to p0e 3 not connected connected *: to disconnect the pull-up resistor in the output mode, clear the corresponding bit of the p0ebpu register. m pd17215, 17216, 17217, 17218 28 4. clock generator circuit 4.1 instruction execution time (cpu clock) selection the m pd17215 is equipped with a clock oscillator circuit that supplies clocks to the cpu and hardware peri-pherals. instruction execution time can be changed in two steps (ordinary mode and high-speed mode) without changing the oscillation frequency. to change the instruction execution time, change the mode of sysck (rf: address 02h) of the register file by using the poke instruction. note, that the mode is actually only changed when the instruction next to the poke instruction has been executed. when using the high-speed mode, pay attention to the supply voltage. (refer to 13. electrical specifications .) at reset, the ordinary mode is set. 32 10 0 0 0 sysck address: rf : 02h sysck on reset: 0h r/w: r/w 0 1 selects instruction execution time ordinary mode 32/f (8 s) m high-speed mode 16/f (4 s) m x x figures in ( ): indicate figures when system clock f = 4 mhz. x m pd17215, 17216, 17217, 17218 29 5. 8-bit timer and remote controller carrier generator circuit the m pd17215 is equipped with the 8-bit timer which is mainly used to generate the leader pulse of the remote controller signal, and to output codes. 5.1 configuration of 8-bit timer (with modulo function) figure 5-1 shows the configuration of the 8-bit timer. as shown in this figure, the 8-bit timer consists of an 8-bit counter (tmc), an 8-bit modulo register (tmm), a comparator that compares the value of the timer with the value of the modulo register, and a selector that selects the operation clock of the 8-bit timer. to start/stop the 8-bit timer, and to reset the 8-bit counter, tmen (address 33h, bit 3) and tmres (address 33h, bit 2) of the register file are used. to select the operation clock of the 8-bit timer, use tmck1 (address 33h, bit 1) and tmck0 (address 33h, bit 0) of the register file. the value of the 8-bit counter is read by using the get instruction through dbf (data buffer). no value can be set to the 8-bit counter. a value is set to the modulo register by using the put instruction through dbf. the value of the modulo register cannot be read. when the value of the counter coincides with that of the modulo register, an interrupt flag (irqtm: address 3fh, bit 0) of the register file is set. 76543210 tmc tmm address on reset r/w peripheral register: 05h 00h r address on reset r/w peripheral register: 06h ffh w 8-bit counter 76543210 8-bit modulo register caution: do note clear tmm to 0 (irqtm is not set). m pd17215, 17216, 17217, 17218 30 fig. 5-1 configuration of 8-bit timer and remote controller carrier generator circuit data buffer internal bus tmen tmres tmck1 tmck0 selector rf : 33h 8-bit timer remote controller carrier generator circuit f /32 x f /64 x f /256 x 8-bit modulo register tmm comparator 8-bit counter tmc irqtm 7-bit counter f /2 x comparator 7-bit modulo register nrzltmm 7-bit counter comparator 7-bit modulo register nrzhtmm r s q nrzbf nrz rf : 11h rf : 12h rem fixed 0 bit 7 bit 7 sw remark: tmm, tmc, nrzltmm, and nrzhtmm are peripheral registers. m pd17215, 17216, 17217, 17218 31 5.2 function of 8-bit timer (with modulo function) 32 10 tmen tmres tmck1 tmck0 address rf : 33h tmres on reset 8h r/w r/w 0 1 8-bit timer reset flag data read out is always "0" resets 8-bit counter and irqtm tmen 0 1 8-bit timer count enable flag stops 8-bit timer count operation enable 8-bit timer count operation (falling edge) tmck1 tmck0 00 01 10 11 8-bit timer clock source selection count clock: f x /32 (measurement time range: 8 s to 2.048 ms) m count clock: f x /64 (measurement time range: 16 s to 4.096 ms) m count clock : f x /256 (measurement time range: 64 s to 16.384 ms) m remote control carrier generation circuit output value indicated by parentheses is for when ( ): f (system clock) = f = 4mhz sys x *1 *2 nrzltmm address on reset r/w peripheral register: 03h undefined r/w 76543210 7-bit modulo register bit 7 0 1 output control of rem pin when nrz = 1, carrier output to rem pin when nrz = 1, high-level output to rem pin nrzhtmm address on reset r/w peripheral register: 04h undefined r/w 76543210 7-bit modulo register bit 7 fixed to 0 0 *1: when the stop mode is released, bit 3 must be set. 2: bit 2 is a write-only bit. m pd17215, 17216, 17217, 17218 32 5.3 carrier generator circuit for remote controller m pd17215 is provided with a carrier generator circuit for the remote controller. the remote controller carrier generator circuit consists of a 7-bit counter, nrz high-level period setting modulo register (nrzhtmm), and nrz low-level period setting modulo register (nrzltmm). the high-level and low-level periods are set in the corresponding modulo registers through the dbf to determine the carrier duty factor and carrier frequency. the system clock (f x ) is divided by two and is input to the 7-bit counter. therefore, when a 4-mhz oscillator is used, 2 mhz (0.5 m s) is input to the counter as the clock; when a 32-khz oscillator (f xt ) is used, 16 khz is input. the nrz high-level output period setting modulo register is called nrzhtmm, and the nrz low-level period setting modulo register is called nrzltmm. data is written to these registers by the put instruction. the contents for these register are read by the get instruction. bit 7 of nrzltmm specifies whether the carrier or high level is output to the rem pin. to output the carrier, be sure to clear bit 7 to 0. 5.3.1 remote controller signal output control the rem pin, which outputs the carrier, is controlled by bits nrz and nrzbf for the register file and timer 0. while the nrz content is 1, the clock generated by the remote controller carrier generator circuit is output to the rem pin; while the nrz content is 0, the rem pin outputs a low level. the nrzbf content is automatically transferred to nrz by the interrupt signal generated by timer 0. if data is set in nrzbf in advance, the rem pin status changes in synchronization with the timer 0 counting operation. if the interrupt signal is generated from timer 0 with the rem pin at the high level, nrz being 1, and the carrier clock at the high level, the rem pin output is not in accordance with the updated content of nrz, until the carrier clock goes low. this processing is useful for holding the high level pulse width from the output carrier constant (refer to the figure below). when the content of nrz is 0, the remote controller carrier generator circuit stops. however, if the clock for timer 0 is output from the remote controller carrier generator circuit, the clock continues to operate, even when the nrz content becomes 0. an actual example showing a remote controller signal output to the rem pin is presented below. when bit 7 of nrzltmm is 0 (carrier output) nrz rem max. 500 ns (delay)* (f = 4 mhz) rem pin does not go low until carrier goes low even if nrz becomes 0 x *: value when (tmck1, tmck0) (1, 1). when (tmck1, tmck0) = (1, 1), the value differs depending on how nrz is manipulated. if nrz is set by an instruction, the width of the first high-level pulse may be shortened. if nrz is set by data transferred from nrzbf, the high-level pulse is delayed by the low-level pulse of the carrier clock. m pd17215, 17216, 17217, 17218 33 when bit 7 of nrzltmm is 0 (carrier not output) 32 10 0 0 0 nrz address rf : 12h nrz on reset 0h r/w r/w 0 1 nrz data outputs low level to rem pin outputs a carrier to rem pin or high level output 32 10 0 0 0 nrzbf address rf : 11h nrzbf on reset 0h r/w r/w 0 1 nrz data output next nrz buffer bit. transfered to nrz by interrupt signal for 8-bit timer. nrz rem setting carrier frequency and duty factor where the system clock frequency is f x and carrier frequency is f c : l (division ratio) = f x /(2 f c ) l is divided into m:n and is set in the modulo registers as follows: high-level period set value = { l m/(m + n)} - 1 low-level period set value = { l n/(m + n)} - 1 example: where f c = 38 khz, duty factor (high-level period) = 1/3, and f x = 4 mhz, l = 4 mhz/(2 x 38 khz) = 52.6 m:n = 1:2 from the above, the value of the modulo register is: high-level period = 17 low-level period = 34 therefore, the carrier frequency is 37.74 khz. m pd17215, 17216, 17217, 17218 34 table 5-1 carrier frequency list (f x = 4 mhz) set value nrzhtmm 00h 01h 04h 09h 0fh 0fh 11h 11h 19h 3fh 7fh nrzltmm 00h 02h 04h 09h 10h 21h 21h 22h 35h 3fh 7fh 1/f c ( m s) 1.0 2.5 5.0 10.0 16.5 25.0 26.0 26.5 40.0 64.0 120.0 f c (khz) 1000 400 200 100 60.6 40.0 38.5 37.7 25.0 15.6 7.8 duty 1/2 2/5 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/2 1/2 t h ( m s) 0.5 1.0 2.5 5.0 8.0 8.0 9.0 9.0 13.0 32.0 64.0 t l ( m s) 0.5 1.5 2.5 5.0 8.0 17.0 17.0 17.5 27.0 32.0 64.0 rem (f c ) t h t l 1/f c m pd17215, 17216, 17217, 17218 35 5.3.2 countermeasures against noise during transmission (carrier output) when a signal is transmitted from the transmitter of a remote controller, a peak current of 0.5 to 1 a may flow through the infrared led. since two batteries are usually used as the power source of the transmitter, several w of equivalent resistance (r) exists in the power source as shown in fig. 5-2. this resistance increases to 10 to 20 w if the supply voltage drops to 2 v. while the carrier is output from the rem pin (while the infrared led lights), therefore, a high-frequency noise may be generated on the power lines due to the voltage fluctuation that may take place especially during switching. to minimize the influence on the microcontroller of this high-frequency noise, take the following measures: <1> separate the power lines of the microcontroller from the power lines of the infrared led with the terminals of the batteries at the center. use thick power lines and keep the wiring short. <2> locate the oscillator as close as possible to the microcontroller and shield it with gnd lines (as indicated by the shaded portion in the figure below). <3> locate the capacitor for stabilization of the power supply closely to the power lines of the microcontroller. also, use a capacitor to eliminate high-frequency noise. <4> to prevent data from changing, do not execute an interrupt that requires read/write processing and stack, such as key scan interrupt, and the call/ret instruction, while the carrier is output. <5> to improve the reliability in case of program hang-up, use the watchdog timer (connect the wdout and reset pins). fig. 5-2 example of countermeasures against noise 0.5 C 1 a infrared led rem v reset wdout dd microcomputer + C r batteries v ss remarks 1: the int and reset pins are multiplexed with test pins (refer to 1.4 notes on using of int and reset pins ). 2: in this figure, the reset pin is connected to a pull-up resistor by mask option. m pd17215, 17216, 17217, 17218 36 6. basic interval timer/watchdog timer the basic interval timer has a function to generate the interval timer interrupt signal and watchdog timer reset signal. 6.1 source clock for basic interval timer the system clock (f x ) is divided, to generate the source clock for the basic interval timer. the input clock frequency for the basic interval timer is f x /2 7 . when the cpu is set in the stop mode, the basic interval timer also stops. 6.2 controlling basic interval timer the basic interval timer is controlled by the bits on the register file. that is, the basic interval timer is reset by btmres. the frequency for the interrupt signal, output by the basic interval timer, is selected by btmmd, and the watchdog timer is reset by wdtres. fig. 6-1 basic interval timer configuration system clock f x 1/2 divider 7 1/2 divider 11 1/2 divider 1/2 divider 1/2 divider btmres wdtres btmck irqbtm wdout selector b f /2 18 x f /2 20 x m pd17215, 17216, 17217, 17218 37 32 10 wdtres btmck btmres 0 address rf : 03h btmres on reset 0h r/w r/w* 0 1 basic interval timer reset data read out is always "0" writing "1" resets basic interval timer btmck 0 1 basic interval timer mode selection generates interrupt signal irqbtm every f /2 wdtres 0 1 watchdog timer reset data read out is always "0" writing "1" resets watchdog timer (f /2 counter) x 20 generates interrupt signal irqbtm every f /2 x 18 x 21 *: bits 1 and 3 are write-only bits. m pd17215, 17216, 17217, 17218 38 6.3 operation timing for watchdog timer the basic interval timer can be used as a watchdog timer. unless the watchdog timer is reset within a fixed time*, it judges that the program has hung up, and the m pd17215 is reset. it is therefore necessary to reset through programming the watchdog timer with in a fixed time. the watchdog timer can be reset by setting wdtres to 1. *: fixed time: approx. 340 ms (at 4 mhz) coutions 1: the watchdog timer cannot be reset in the shaded range in fig. 6-2. therefore, set wdtres before both the f x /2 21 and f x /2 20 signals go high. 2: refer to 9. reset for the wdout pin function. fig. 6-2 watchdog timer operation timing f /2 x 18 intbtm (f /2 ) intbtm (f /2 ) wdout wdtres watchdog timer reset signal wdout output goes low if wdtres is not set setting wdtres at this timing is invalid f /2 x 19 f /2 x 20 f /2 x 21 x 20 x 18 m pd17215, 17216, 17217, 17218 39 7. interrupt functions 7.1 interrupt sources m pd17217 is provided with three interrupt sources. when an interrupt has been accepted, the program execution automatically branches to a predetermined address, which is called a vector address. a vector address is assigned to each interrupt source, as shown in table 7-1. table 7-1 vector address priority interrupt source ext/int vector address 1 8-bit timer internal 0003h 2 int pin rising and falling edges external 0002h 3 basic interval timer internal 0001h when more than one interrupt request is issued at the same time, the interrupts are accepted in sequence, starting from the one with the highest priority. whether an interrupt is enabled or disabled is specified by the ei or di instruction. the basic condition under which an interrupt is accepted is that the interrupt is enabled by the ei instruction. while the di instruction is executed, or while a n interrupt is accepted, the interrupt is disabled. to enable accepting an interrupt after the interrupt has been processed, the ei instruction must be executed before the reti instruction. accepting the interrupt is enabled by the ei instruction after the instruction next to the ei instruction ha s been executed. therefore, no interrupt can be accepted between the ei and reti instructions. caution: in interrupt processing, only the bcd, cmp, cy, z, ixe flags are automatically saved to the stack by the hardware, to a maximum of three levels. also, within the interrupt processing contents, when peripheral hardware (timer, a/d converter, etc. ) is accessed, the dbf and wr contents are not saved by the hardware. accordingly, it is recommended that at the beginning of interrupt processing dbf and wr be saved by software to ram, and immediately before finishing interrupt processing the saved contents be returned to thier original location. m pd17215, 17216, 17217, 17218 40 7.2 hardware of interrupt control circuit this section describes the flags of the interrupt control circuit. (1) interrupt request flag and interrupt enable flag the interrupt request flag (irqxxx) is set to 1 when an interrupt request is generated, and is automatically cleared to 0 when the interrupt processing is excuted. an interrupt enable flag (ipxxx) is provided to each interrupt request flag. when the ipxxx flag is 1, the interrupt is enabled; when it is 0, the interrupt is disabled. (2) ei/di instruction whether an accepted interrupt is executed or not is specified by the ei or di instruction. when the ei instruction is executed, inte (interrupt enable flag), which enables the interrupt, is set to 1. the inte flag is not registered on the register file. consequently, the status of this flag cannot be checked by an instruction. the di flag clears the inte flag to 0 to disable all the interrupts. the inte flag is also cleared to 0 at reset, disabling all the interrupts. table 7-2 interrupt request flags and interrupt enable flag interrupt signal setting interrupt request flag interrupt request flag enable flag irqtm reset by 8-bit timer. iptm irq set when edge of int pin input signal is detected ip irqbtm reset by basic interval timer. ipbtm m pd17215, 17216, 17217, 17218 41 7.2.1 int this flag reads the int pin status. when a high level is input to the int pin, this flag is set to 1; when a low level is input, the flag is reset to 0. 32 10 0 0 0 int address rf : 0fh int on reset undefined r/w r 0 1 int pin level detection int pin : low level int pin : high level 7.2.2 ieg this pin selects the interrupt edge to be detected on the int pin. when this flag is 0, the interrupt is detected at the rising edge; when it is 1, the interrupt is detected at the falling e dge. 32 10 0 0 0 ieg address rf : 1fh ieg on reset 0h r/w r/w 0 1 int pin interrupt detection edge selection rising edge of int pin falling edge of int pin m pd17215, 17216, 17217, 17218 42 7.2.3 interrupt enable flag this flag enables each interrupt source. when this flag is 1, the corresponding interrupt is enabled; when it is 0, the interrupt is disabled. 32 10 0 ipbtm ip iptm address rf : 2fh iptm on reset 0h r/w r/w 0 1 8-bit timer interrupt enable flag disables interrupt acceptance by 8-bit timer enables interrupt acceptance by 8-bit timer ip 0 1 int pin interrupt enable flag disables interrupt acceptance by int pin input ipbtm 0 1 basic interval timer interrupt enable flag disables interrupt acceptance by basic interval timer enables interrupt acceptance by basic interval timer enables interrupt acceptance by int pin input m pd17215, 17216, 17217, 17218 43 7.2.4 irq this is an interrupt request flag that indicates the interrupt request status. when an interrupt request is generated, this flag is set to 1. when the interrupt has been accepted, the interrupt request flag is reset to 0. the interrupt request flag can be read or written by the program. therefore, when it is set to 1, an interrupt can be generated by the software. by writing 0 to the flag, the interrupt pending status can be canceled. 32 10 0 0 0 irqbtm address rf : 3dh irqbtm on reset 0h r/w r/w 0 1 basic interval timer interrupt request flag basic interval timer interrupt request has been made. 32 10 0 0 0 irq address rf : 3eh irq on reset 0h r/w r/w 0 1 int pin interrupt request flag interrupt request has not been made. interrupt request has been made at rising edge or falling edge of int input. 32 10 0 0 0 irqtm address rf : 3fh irqtm on reset 1h* r/w r/w 0 1 8-bit timer interrupt request flag 8-bit timer interrupt request has been made. interrupt request has not been made. interrupt request has not been made. *: 1h is also set after releasing stop mode. m pd17215, 17216, 17217, 17218 44 7.3 interrupt sequence if irqxxx flag is set to 1 when ipxxx flag is 1, interrupt processing is started after the instruction cycle of the instruc tion executed when irqxxx flag was set has ended. since the movt instruction, ei instruction, and the instruction which matches the condition to skip use two instruction cycles, the interrupt enabled while this instruction is executed is processed after the second instruction cycle is over. if ipxxx flag is 0, the interrupt processing is not performed even if irqxxx flag is set, until ipxx flag is set. if two or more interrupts are enabled simultaneously, the interrupts are processed starting from the one with the highest priority. the interrupt with the lower priority is kept pending until the processing of the interrupt with the higher priority is finished. 7.3.1 operations when interrupt is accepted when an interrupt has been accepted, the cpu performs processing in the following sequence: clears irq corresponding to inte flag and accepted interrupt decrements value of stack pointer by 1 (sp-1) saves contents of program counter to stack addressed by stack pointer loads vector address to program counter save contents of psword to interrupt stack register one instruction cycle is required to perform the above processing. m pd17215, 17216, 17217, 17218 45 7.3.2 returning from interrupt processing routine to return from an interrupt processing routine, use the reti instruction. then the following processing is executed within an instruction cycle. loads contents of interrupt stack register to psword increments value of stack pointer by 1 loads contents of stack addressed by stack pointer to program counter to enable an interrupt after the processing of an interrupt has been finished, the ei instruction must be executed immediately before the reti instruction. accepting the interrupt is enabled by the ei instruction after the instruction next to the ei instruction has been executed. therefore, the interrupt is not accepted between the ei and reti instructions. m pd17215, 17216, 17217, 17218 46 8. standby functions m pd17215 is provided with halt and stop modes as standby functions. by using the standby function, current dissipation can be reduced. in the halt mode, the program is not executed, but the system clock f x is not stopped. this mode is main- tained, until the halt mode release condition is satisfied. in the stop mode, the system clock is stopped and program execution is stopped. this mode is maintained, until the stop mode release condition is satisfied. the halt mode is set, when the halt instruction has been executed. the stop mode is set, when the stop instruction has been executed. 8.1 halt mode in this mode, program execution is temporarily stopped, with the main clock continuing oscillating, to reduce current dissipation. use the halt instruction to set the halt mode. the halt mode releasing condition can be specified by the operand for the halt instruction, as shown in table 8-1. after the halt mode has been released, the operation is performed as shown in table 8-1 and figure 8-2. caution: do not execute an instruction that clears the interrupt request flag (irqxxx) for which the interrupt enable flag (ipxxx) is set immediately before the halt 8h instruction; otherwise, the halt mode may not be set. table 8-1 halt mode releasing conditions operand value releasing conditions 0010b (02h) when interrupt request (irqtm) occurs for 8-bit timer <1> when interrupt request (irqtm, irqwtm, or irq), whose interrupt enable flag (iptm, 1000b (08h) ipbtm, or ip) is set, occurs <2> when any of p0a 0 -p0a 3 and p0b 0 -p0b 3 pins goes low other than above inhibited table 8-2 operations after halt mode release (1/2) (a) halt 08h halt mode released by: interrupt status interrupt enable flag operations after halt mode release low-level input of p0a 0 -p0a 3 , dont care dont care instruction next to halt is executed p0b 0 -p0b 3 disabled standby mode is not released di when release condition is enabled instruction next to halt is executed satisfied by interrupt disabled standby mode is not released ei enabled branches to interrupt vector address m pd17215, 17216, 17217, 17218 47 table 8-2 operations after halt mode release (2/2) (b) halt 02h halt mode released by: interrupt status interrupt enable flag operations after halt mode release disabled di enabled 8-bit timer disabled ei enabled branches to interrupt vector address 8.2 halt instruction execution conditions the halt instruction can be executed, only under special conditions, as shown in table 8-3, to prevent the program from hangup. if the conditions in table 8-3 are not satisfied, the halt instruction is treated as an nop instruction. table 8-3 halt instruction execution conditions operand value execution conditions 0010b (02h) when all interrupt request flags (irqtm) of 8-bit timer are reset <1> when interrupt request flag is reset, corresponding to interrupt whose interrupt enable 1000b (08h) flag (iptm, ipbtm, or ip) is set <2> when high level is input to all p0a 0 -p0a 3 and p0b 0 -p0b 3 pins other than above inhibited 8.3 stop mode in the stop mode, the system clock (f x ) oscillation is stopped and the program execution is stopped to minimize current dissipation. to set the stop mode, use the stop instruction. the stop mode releasing condition can be specified by the stop instruction operand, as shown in table 8-4. after the stop mode has released, the operation is performed as follows: <1> resets irqtm. <2> starts the basic interval timer and watchdog timer (does not reset). <3> resets and starts the 8-bit timer. <4> executes the instruction next to [stop 8h] when the current value of the 8-bit counter coincides with the value of the modulo register (irqtm is set). instructions are executed from the instruction next to the halt instruction. m pd17215, 17216, 17217, 17218 48 the m pd17215 oscillator circuit is stopped, when the stop instruction has been executed (i.e., in the stop mode). oscillation is not resumed, until the stop mode is released. after the stop mode has been released, the halt mode is set. set the time required to release the halt mode by using the timer with modulo function. the time that elapses, after the stop mode has been released by occurrence of an interrupt, until an operation mode is set, is shown in the following table. time required to set operation mode 8-bit modulo register set value after stop mode release (tmm) at 4 mhz 40h 4.160 ms (64 m s 65) ffh 16.384 ms (64 m s 256) remark: set the 8-bit modulo timer before executing stop instruction. caution: do not execute an instruction that clears the interrupt request flag (irqxxx) for which the interrupt enable flag (ipxxx) is set immediately before the stop 8h instruction; otherwise, the stop mode may not be set. table 8-4 stop mode releasing conditions operand value releasing conditions 1000b (08h) when any of p0a 0 -p0a 3 and p0b 0 -p0b 3 pins goes low others inhibited m pd17215, 17216, 17217, 17218 49 8.4 stop instruction execution conditions the stop instruction can be executed, only under special conditions, as shown in table 8-5, to prevent the program from hangup. if the conditions in table 8-5 are not satisfied, the stop instruction is treated as an nop instruction. table 8-5 stop instruction execution conditions operand value execution conditions 1000b (08h) high level input for all p0a 0 -p0a 3 and p0b 0 -p0b 3 pins others inhibited 8.5 releasing standby mode operations for releasing the stop and halt modes will be as shown in fig. 8-1. fig. 8-1 operations after standby mode release (a) releasing stop mode by interrupt stanby release signal stop instruction wait (time set by tmm) operation mode stop mode halt mode operation mode clock oscillation oscillation stops oscillation (b) releasing halt mode by interrupt halt instruction stanby release signal clock operation mode operation mode halt mode oscillation remark: the dotted line indicates the operation to be performed when the interrupt request, releasing the standby mode, has been accepted. m pd17215, 17216, 17217, 17218 50 9. reset 9.1 reset by reset signal input when a low-level signal more than 50 m s is input to the reset pin, m pd17215 is reset. when the system is reset, the oscillator circuit remains in the halt mode and then enters an operation mode, like when the stop mode has been released. the wait time, after the reset signal has been removed, is 16.384 ms (f x = 4 mhz). on power application, input the reset signal at least once because the internal circuitry operations are not stable. when m pd17215 is reset, the following initialization takes place: (1) program counter is reset to 0. (2) flags in the register file are initialized to their default values (for the default values, refer to fig. 11-1 register files). (3) the default value (0320h) is written to the data buffer (dbf). (4) the hardware peripherals are initialized. (5) the system clock (f x ) stops oscillation. when the reset pin is made high, the system clock starts oscillating, and the program execution starts from address 0 about 16 ms (at 4 mhz) later. fig. 9-1 reset operation by reset input reset wait starts from address 0h (about 16 ms at 4 mhz) operation mode or standby mode halt mode operation mode oscillation stops 9.2 reset by watchdog timer (connect reset and wdout pins) when the watchdog timer operates during program execution, a low level is output to the wdout pin, and the program counter is reset to 0. if the watchdog timer is not reset for a fixed period of time, the program can be restarted from address 0h. program so that the watchdog timer is reset at intervals of within 340 ms (at f x = 4 mhz) (set the wdtres flag). m pd17215, 17216, 17217, 17218 51 9.3 reset by stack pointer (connect reset and wdout pins) when the value of the stack pointer reaches 6h or 7h during program execution, a low level is output to the wdout pin, and the program counter is reset to 0. if the nesting level of the interrupt or subroutine call exceeds 5 (stack over flow), or if the return instruction is executed without correspondence between call and return (ret) instructions established, then regardless of a stack level of 0 (stack underflow), the program can be restarted from address 0h. table 9-1 status of each hardware after reset hardware reset input during reset input standby mode during operation program counter (pc) 0000h 0000h port input/output input input output latch 0 0 data memory (ram) general-purpose data memory retains previous undefined (except dbf, port register) status dbf 0320h 0320h system register (sysreg) 0 0 wr retains previous undefined status control register refer to fig. 11-1 register files 8-bit timer counter (tmc) 00h 00h modulo register (tmm) ffh ffh remote controller carrier nrz high level period setting modulo register retains previous undefined generator (nrzhtmm) status nrz low level period setting modulo register (nrzltmm) basic interval timer/watchdog timer counter 00h 00h 10. low-voltage detector circuit (connect reset and wdout pins) the low-voltage detector circuit outputs a low level from the wdout pin for initialization (reset) to prevent program hang- up that may take place when the batteries are replaced, if the circuit detects a low voltage. a drop in the supply voltage is detected if the status of t a = -10 to +85 c, v dd = 0.8 to 2.2 v lasts for 1 ms or longer. note, however, that 1 ms is the guaranteed value and that the microcontroller may be reset even if the above low-voltage condition lasts for less than 1 ms. although the voltage at which the the reset function is effected ranges from 0.8 to 2.2 v, the program counter is prevented from hang-up even if the supply voltage drops until the reset function is effected, if the instruction execution time is from 8 to 32 m s. note that some oscillators stop oscillating before the reset function is effected. the low-voltage detector circuit can be set arbitrarily by the mask option. m pd17215, 17216, 17217, 17218 52 caution: connect a diode and a capacitor to the reset pin as shown below to stabilize the operation. v reset dd wdout micro- computer remark: in this figure, the reset pin is connected to a pull-up resistor by the mask option. 11. assembler reserved words 11.1 mask option directives when developing the m pd17215 program, mask options must be specified by using mask option directives in the program. the reset pin for m pd17215 requires a mask option to be specified. 11.1.1 option and endop directives that portion of the program enclosed by the option and endop directives is called a mask option definition block. this block is described in the following format: description: symbol mnemonic operand comment [label: ] option [;comment] : : : endop 11.1.2 mask option definition directives table 19-1 lists the directives that can be used in the mask option definition block. here is an example of mask option definition: description format: symbol field mnemonic field operand field comment field option optres pullup ; reset pin has pull-up resistors. optpoc usepoc ; internal low-voltage detector circuit endop m pd17215, 17216, 17217, 17218 53 name directive operands table 11-1 mask option definition directives 1st 2nd 3rd 4th operand operand operand operand mask option of reset pullup reset optres 1 (w/pull-up resistor) open (w/o pull-up resistor) 11.2 reserved symbols the symbols defined by the m pd17215 device file are listed in table 11-2. the defined symbols are the following register file names, port names, and peripheral hardware names. 11.2.1 register file the names of the symbols assigned to the register file are defined. these registers are accessed by the peek and poke instructions through the window register (wr). fig. 11-1 shows the register file. 11.2.2 registers and ports on data memory the names of the registers assigned at addresses 00h through 7fh on the data memory and the names of ports assigned to address 70h and those that follow, and system register names are defined. fig. 11-2 shows the data memory configuration. 11.2.3 peripheral hardware the names of peripheral hardware accessed by the get and put instructions are defined. table 11-3 shows the peripheral hardware. usepoc (low-voltage detector circuit provided) nousepoc (low-voltage detector circuit not provided) poc optpoc 1 m pd17215, 17216, 17217, 17218 54 table 11-2 reserved symbols (1/2) symbol name attribute value r/w description dbf3 mem 0.0ch r/w bits 15-12 of data buffer dbf2 mem 0.0dh r/w bits 11-8 of data buffer dbf1 mem 0.0eh r/w bits 7-4 of data buffer dbf0 mem 0.0fh r/w bits 3-0 of data buffer ar3 mem 0.74h r bits 15-12 of address register ar2 mem 0.75h r/w bits 11-8 of address register ar1 mem 0.76h r/w bits 7-4 of address register ar0 mem 0.77h r/w bits 3-0 of address register wr mem 0.78h r/w window register bank mem 0.79h r bank register ixh mem 0.7ah r bits 11-8 of index register mph mem 0.7ah r bits 7-4 of memory pointer mpe flg 0.7ah.3 r/w memory pointer enable flag ixm mem 0.7bh r/w bits 7-4 of index register mpl mem 0.7bh r/w bits 3-0 of memory pointer ixl mem 0.7ch r/w bits 3-0 of index register rph mem 0.7dh r bits 7-4 of register pointer rpl mem 0.7eh r/w bits 3-0 of register pointer psw mem 0.7fh r/w program status word bcd flg 0.7eh.0 r/w bcd flag cmp flg 0.7fh.3 r/w compare flag cy flg 0.7fh.2 r/w carry flag z flg 0.7fh.1 r/w zero flag ixe flg 0.7fh.0 r/w index register enable flag p0a0 flg 0.70h.0 r/w bit 0 of port 0a p0a1 flg 0.70h.1 r/w bit 1 of port 0a p0a2 flg 0.70h.2 r/w bit 2 of port 0a p0a3 flg 0.70h.3 r/w bit 3 of port 0a p0b0 flg 0.71h.0 r/w bit 0 of port 0b p0b1 flg 0.71h.1 r/w bit 1 of port 0b p0b2 flg 0.71h.2 r/w bit 2 of port 0b p0b3 flg 0.71h.3 r/w bit 3 of port 0b p0c0 flg 0.72h.0 r/w bit 0 of port 0c p0c1 flg 0.72h.1 r/w bit 1 of port 0c p0c2 flg 0.72h.2 r/w bit 2 of port 0c p0c3 flg 0.72h.3 r/w bit 3 of port 0c p0d0 flg 0.73h.0 r/w bit 0 of port 0d p0d1 flg 0.73h.1 r/w bit 1 of port 0d p0d2 flg 0.73h.2 r/w bit 2 of port 0d p0d3 flg 0.73h.3 r/w bit 3 of port 0d m pd17215, 17216, 17217, 17218 55 table 11-2 reserved symbols (2/2) symbol name attribute value r/w description p0e0 flg 0.6fh.0 r/w bit 0, port 0e p0e1 flg 0.6fh.1 r/w bit 1, port 0e p0e2 flg 0.6fh.2 r/w bit 2, port 0e p0e3 flg 0.6fh.3 r/w bit 3, port 0e sp mem 0.81h r/w stack pointer sysck flg 0.82h.0 r/w selects system clock wdtres flg 0.83h.3 r/w resets watchdog timer btmck flg 0.83h.2 r/w selects basic interval timer mode btmres flg 0.83h.1 r/w resets basic interval timer mode int flg 0.8fh.0 r int pin status nrzbf flg 0.91h.0 r/w nrz buffer data nrz flg 0.92h.0 r/w nrz data p0ebpu0 flg 0.97h.0 r/w pull-up resistor setting flag for p0e 0 p0ebpu1 flg 0.97h.1 r/w pull-up resistor setting flag for p0e 1 p0ebpu2 flg 0.97h.2 r/w pull-up resistor setting flag for p0e 2 p0ebpu3 flg 0.97h.3 r/w pull-up resistor setting flag for p0e 3 ieg flg 0.9fh.0 r/w selects interrupt edge for int pin p0ebio0 flg 0.0a7h.0 r/w i/o setting flag, p0e 0 p0ebio1 flg 0.0a7h.1 r/w i/o setting flag, p0e 1 p0ebio2 flg 0.0a7h.2 r/w i/o setting flag, p0e 2 p0ebio3 flg 0.0a7h.3 r/w i/o setting flag, p0e 3 ipbtm flg 0.0afh.2 r/w interrupt enable flag of basic interval timer ip flg 0.0afh.1 r/w int interrupt enable flag iptm flg 0.0afh.0 r/w 8-bit timer interrupt enable flag tmen flg 0.0b3h.3 r/w 8-bit timer count enable flag tmres flg 0.0b3h.2 r/w 8-bit timer reset flag tmck1 flg 0.0b3h.1 r/w selects clock source for 8-bit timer tmck0 flg 0.0b3h.0 r/w selects clock source for 8-bit timer irqbtm flg 0.0bdh.0 r/w basic interval timer interrupt request flag irq flg 0.0beh.0 r/w int interrupt request flag irqtm flg 0.0bfh.0 r/w 8-bit timer interrupt request flag tmc dat 05h r 8-bit counter tmm dat 06h w 8-bit modulo register nrzltmm dat 03h r/w nrz low level period setting modulo register nrzhtmm dat 04h r/w nrz high level period setting modulo register ar dat 40h r/w address register m pd17215, 17216, 17217, 17218 56 fig. 11-1 register files (1/2) column address row address 01234567 ******** bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 0 1 0 1 0 0 0 sysck 0 0 0 0 wdtres btmck btmres 0 sp 0 0 0 0 0 0 0 0 0 0 0 nrz 0 0 0 0 0 0 0 nrzbf 0 1 2 3 tmen tmres tmck1 tmck0 1 0 0 0 0 0 0 0 0 0 0 0 p0ebpu3 p0ebpu2 p0ebpu1 p0ebpu0 p0ebio3 p0ebio2 p0ebio1 p0ebio0 *: on reset fig. 11-2 data memory configuration 0123 4567 89abcdef 0 1 2 3 4 5 6 7 row address system register dbf p0e -p0e 03 dbf3dbf2dbf1dbf0 ar3 ar2 ar1 ar0 wr bank ixh ixm ixl rph rpl psw p0d -p0d 03 column address p0c -p0c 03 p0b -p0b 03 p0a -p0a 03 m pd17215, 17216, 17217, 17218 57 fig. 11-1 register files (2/2) column address row address 89abcdef ******** bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 p 0 0 0 1 0 0 0 int 0 0 0 irqtm 0 0 0 ieg 0 ipbtm ip iptm 0 0 0 0 0 0 0 irq 0 0 0 0 0 0 0 irqbtm *: on reset p: when int pin is high level, 1 or when int pin is low level, 0. table 11-3 peripheral hardwre name address valid bit description tmc 05h 8 8-bit timer count register tmm 06h 8 8-bit timer modulo register nrzltmm 03h 8 low level period setting modulo register for remote controller carrier generation nrzhtmm 04h 8 high level period setting modulo register for remote controller carrier generation ar 40h 16 address register m pd17215, 17216, 17217, 17218 58 01 12. instruction set 12.1 instruction set outline b 15 b 14 -b 11 bin. hex. 0 0 0 0 0 add r, m add m, #n4 0 0 0 1 1 sub r, m sub m, #n4 0 0 1 0 2 addc r, m addc m, #n4 0 0 1 1 3 subc r, m subc m, #n4 0 1 0 0 4 and r, m and m, #n4 0 1 0 1 5 xor r, m xor m, #n4 0 1 1 0 6 or r, m or m, #n4 inc ar inc ix movt dbf, @ar br @ar call @ar ret retsk ei di 0 1 1 1 7 reti push ar pop ar get dbf, p put p, dbf peek wr, rf poke rf, wr rorc r stop s halt h nop 1 0 0 0 8 ld r, m st m, r 1 0 0 1 9 ske m, #n4 skge m, #n4 1 0 1 0 a mov @r, m mov m, @r 1 0 1 1 b skne m, #n4 sklt m, #n4 1 1 0 0 c br addr (page 0) call addr 1 1 0 1 d br addr (page 1) mov m, #n4 1 1 1 0 e br addr (page 2) skt m, #n 1 1 1 1 f br addr (page 3) skf m, #n m pd17215, 17216, 17217, 17218 59 12.2 legend ar : address register asr : address stack register specified by stack pointer addr : program memory address (lower 11 bits) bank : bank register cmp : compare register cy : carry flag dbf : data buffer h : halt releasing condition intef : interrupt enable flag intr : register automatically saved to stack in case of interrupt intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address specified by m r , m c m r : data memory row address (high) m c : data memory column address (low) n : bit position (4 bits) n4 : immediate data (4 bits) page : page (bit 11 and 12 of program counter) pc : program counter p : peripheral address p h : peripheral address (higher 3 bits) p l : peripheral address (lower 4 bits) r : general register column address rf : register file address rf r : register file address (higher 3 bits) rf c : register file address (lower 4 bits) sp : stack pointer s : stop releasing condition wr : window register ( ) : contents addressed by m pd17215, 17216, 17217, 17218 60 group mnemonic operand operation 12.3 list of instruction sets instruction code op code operand r, m (r) (r) + (m) 00000 m r m c r add m, #n4 (m) (m) + n4 10000 m r m c n4 r, m (r) (r) + (m) + cy 00010 m r m c r addition addc m, #n4 (m) (m) + n4 + cy 10010 m r m c n4 ar ar ar +1 00111 000 1001 0000 inc ix ix ix +1 00111 000 1000 0000 r, m (r) (r) C (m) 00001 m r m c r sub subtrac- m, #n4 (m) (m) C n4 10001 m r m c n4 tion r, m (r) (r) C (m) C cy 00011 m r m c r subc m, #n4 (m) (m) C n4 C cy 10011 m r m c n4 r, m (r) (r) M (m) 00110 m r m c r or m, #n4 (m) (m) M n4 10110 m r m c n4 r, m (r) (r) ? (m) 00100 m r m c r logical and m, #n4 (m) (m) ? n4 10100 m r m c n4 r, m (r) (r) " (m) 00101 m r m c r xor m, #n4 (m) (m) " n4 10101 m r m c n4 skt m, #n cmp 0, if (m) ? n = n, then skip 11110 m r m c n skf m, #n cmp 0, if (m) ? n = 0, then skip 11111 m r m c n ske m, #n4 (m)-n4, skip if zero 01001 m r m c n4 skne m, #n4 (m)-n4, skip if not zero 01011 m r m c n4 skge m, #n4 (m)-n4, skip if not borrow 11001 m r m c n4 sklt m, #n4 (m)-n4, skip if borrow 11011 m r m c n4 rotate rorc r 00111 000 0111 r ld r, m (r) (m) 01000 m r m c r st m, r (m) (r) 11000 m r m c r @r, m if mpe = 1 : (mp, (r)) (m) 01010 m r m c r if mpe = 0 : (bank, m r , (r)) (m) transfer mov m, @r if mpe = 1 : (m) (mp, (r)) 11010 m r m c r if mpe = 0 : (m) (bank, m r , (r)) m, #n4 (m) n4 11101 m r m c n4 movt dbf, sp sp C 1, asr pc, pc ar 00111 000 0001 0000 @ar dbf (pc), pc asr, sp sp + 1 cy (r) b3 (r) b2 (r) b1 (r) b0 judge compare m pd17215, 17216, 17217, 17218 61 push ar sp sp C 1, asr ar 00111 000 1101 0000 pop ar ar asr, sp sp +1 00111 000 1100 0000 peek wr, rf wr (rf) 00111 rf r 0011 rf c transfer poke rf, wr (rf) wr 00111 rf r 0010 rf c get dbf, p (dbf) (p) 00111 p h 1011 p l put p, dbf (p) (dbf) 00111 p h 1010 p l m pd17215 pc 10C0 addr 01100 pc 10C0 addr, page 0 01100 m pd17216 pc 10C0 addr, page 1 01101 pc 10C0 addr, page 0 01100 m pd17217 pc 10C0 addr, page 1 01101 branch br addr addr pc 10C0 addr, page 2 01110 pc 10C0 addr, page 0 01100 pc 10C0 addr, page 1 01101 m pD17218 pc 10C0 addr, page 2 01110 pc 10C0 addr, page 3 01111 @ar pc ar 00111 000 0100 0000 addr sp sp C 1, asr pc, 11100 addr pc 10C0 addr, page 0 call @ar sp sp C 1, asr pc, 00111 000 0101 0000 pc ar ret pc asr, sp sp +1 00111 000 1110 0000 retsk pc asr, sp sp +1 and skip 00111 001 1110 0000 reti pc asr, intr intsk, sp sp +1 00111 100 1110 0000 ei intef 1 00111 000 1111 0000 di intef 0 00111 001 1111 0000 stop s stop 00111 010 1111 s other halt h halt 00111 011 1111 h nop no operation 00111 100 1111 0000 group mnemonic operand operation instruction code op code operand sub- routine interrupt m pd17215, 17216, 17217, 17218 62 12.4 assembler (as17k) built-in macro instruction legend flag n: flg type symbol < >: contents in < > can be omitted mnemonic operand operation n sktn flag 1, ...flag n if (flag 1) to (flag n) = all 1, then skip 1 n 4 skfn flag 1, ...flag n if (flag 1) to (flag n) = all 0, then skip 1 n 4 setn flag 1, ...flag n (flag 1) to (flag n) 11 n 4 clrn flag 1, ...flag n (flag 1) to (flag n) 01 n 4 notn flag 1, ...flag n if (flag n) = 0, then (flag n) 1 1 n 4 if (flag n) = 1, then (flag n) 0 initflg m pd17215, 17216, 17217, 17218 63 rem pin total of p0e pins 1 pin (p0e pin) high-level output current* low-level output current* 1 pin (p0c, p0d, p0e, rem or wdout pin) 13. electrical specifications absolute maximum ratings (t a = 25 c) item symbol conditions ratings unit supply voltage v dd C0.3 to +7.0 v input voltage v i C0.3 to v dd +0.3 v output voltage v o C0.3 to v dd +0.3 v peak value C36.0 ma effective value C24.0 ma i oh peak value C7.5 ma effective value C5.0 ma peak value C22.5 ma effective value C15.0 ma peak value 7.5 ma effective value 5.0 ma peak value 22.5 ma effective value 15.0 ma i ol peak value 30.0 ma effective value 20.0 ma operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c power dissipation p d t a = 85 c 180 mw *: calculate effective value by this expression: [effetive value] = [peak value] duty caution: even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure not to exceed or fall below this value when using the product. total of p0c, p0d, wdout pins total of p0e pins m pd17215, 17216, 17217, 17218 64 recommended operating ranges (v dd = 2.0 to 5.5 v, t a = C40 to +85 c) item symbol conditions min. typ. max. unit v dd1 f x = 1 mhz high-speed mode (instruction execution time: 16 m s) 2.0 3.0 5.5 v dd2 ordinary mode (instruction execution time: 8 m s) supply voltage f x = 4 mhz v v dd3 high-speed mode 2.2 3.0 5.5 (instruction execution time: 4 m s) v dd4 f x = 8 mhz high-speed mode 3.5 5.0 5.5 (instruction execution time: 2 m s) oscillation frequency f x 1.0 4.0 8.0 mhz operating temperature t a C40 +25 +85 c low-voltage detector circuit* t cy t a = C10 to +85 c832 m s (mask option) *: reset if the status of v dd = 0.8 to 2.2 v lasts for 1 ms or longer. program hang-up does not occur even if the voltage drops, until the reset function is effected (when the reset pin and wdout pin are connected). some oscillators stop oscillating before the reset function is effected. remark: the region indicated by the broken line in the above figure is the guaranteed operating range in the high-speed mode. f vs v xdd 10 9 8 7 6 5 4 3 2 1 0.4 0 2 2.2 3 4 3.5 5 5.5 6 (v) (mhz) supply voltage: v dd system clock: f (ordinary mode) x operation guaranteed area m pd17215, 17216, 17217, 17218 65 resonator item conditions min. typ. max. unit system clock oscillator circuit characteristics (t a = C40 to +85 c, v dd = 2.0 to 5.5 v) recommended constants oscillation frequency (f x ) * 1 1.0 4.0 8.0 mhz ceramic oscillation after v dd reached stabilization time * 2 min. in oscillation 4ms voltage range * 1: the oscillation frequency only indicates the oscillator characteristics. 2: the oscillation stabilization time is necessary for oscillation to be stabilized, after v dd application or stop mode release. caution: to use a system clock oscillator circuit, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: ? keep wiring length as short as possible. ? do not cross a signal line with some other signal lines. do not route the wiring in the vicinity of lines through which a large current flows. ? always keep the oscillator circuit capacitor ground at the same potential as gnd. do not ground the capacitor to a ground pattern, through which a large current flows. ? do not extract signals from the oscillator circuit. external circuit example x in x out r 1 c 2 c 3 x in x out m pd17215, 17216, 17217, 17218 66 murata mfg, co., ltd. kyocela corp. tdk corp. matsushita electronics com- ponents co., ltd. csb1000j csa2.00mg csa4.00mg csa6.00mg csa8.00mtz cst2.00mg cst4.00mgw cst6.00mgw cst8.00mtw kbr-1000y/f kbr-2.0ms kbr-4.0msa kbr-4.0mks/mws kbr-6.0msa kbr-6.0mks/mws kbr-8.0m pbrc2.00a pbrc3.58a pbrc4.00a pbrc6.00a pbrc8.00a fcr2.0m3 fcr2.0mc3 fcr4.0m5 fcr4.0mc5 ccr4.0mc3 efoec2004a4 efoec4004a4 efoec6004a4 efoec8004a4 efoen2004a4 efoen4004a4 efoen6004a4 efoen8004a4 c1 (pf) 100 30 30 30 30 C C C C 100 47 33 C 33 C 33 47 33 33 33 33 33 C 33 C C C C C C 33 33 33 33 r1 (k w ) 4.7 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C manufacturer product name max. (v) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 min. (v) 2.0 2.0 2.0 2.0 2.1 2.0 2.0 2.0 2.1 2.0 2.0 2.0 2.0 2.2 2.0 2.2 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ceramic resonators oscillation voltage range c2 (pf) 100 30 30 30 30 C C C C 100 47 33 C 33 C 33 47 33 33 33 33 33 C 33 C C C C C C 33 33 33 33 recommended circuit constants m pd17215, 17216, 17217, 17218 67 dc characteristics (v dd = 2.0 to 5.5 v, t a = C40 to +85 c) item symbol conditions min. typ. max. unit v ih1 reset, int pin 0.8v dd v dd v v ih2 p0a, p0b 0.7v dd v dd v high-level input voltage v ih3 p0e 2.0 v v dd < 3.0 v v dd C0.3 v dd v v ih4 p0e 3.0 v v dd 5.5 v v dd C0.5 v dd v v ih5 x in 0.8v dd v dd v v il1 reset, int pin 0 0.2v dd v v il2 p0a, p0b 0 0.3v dd v low-level input voltage v il3 p0e 0 0.35v dd v v il4 x in 0 0.2v dd v high-level input leakage i lih int, reset, v ih = v dd 3.0 m a current p0a, p0b, p0e i lil1 int v il = 0 v C3.0 m a low-level input leakage current i lil2 p0e v il = 0 v w/o C3.0 m a pull-up resistor high-level output leakage i loh p0c, p0d, p0e, v oh = v dd 3.0 m a current wdout i lol1 wdout v ol = 0 v C3.0 m a low-level output leakage current i lol2 p0e v ol = 0 v w/o C3.0 m a pull-up resistor high-level input current i ih x in v ih = v dd 20 m a low-level input current i il x in v il = 0 v C20 m a reset, p0e v dd = 3 v 10% 25 50 100 k w r u1 reset, p0e v dd = 5 v 10% 25 50 100 k w internal pull-up resistor p0a, p0b v dd = 3 v 10% 100 200 400 k w r u2 p0a, p0b v dd = 5 v 10% 100 200 400 k w high-level output current i oh rem v oh = 1.0 v, v dd = 3 v C6.0 C13.0 ma high-level output voltage v oh p0e, rem i oh = C0.5 v ma v dd C0.3 v v ol1 p0c, p0d, rem, i ol = 0.5 ma 0.3 v wdout v ol2 p0e i ol = 1.5 ma 0.3 v low-voltage detector circuit v dt1 0.8 1.6 2.4 v (mask option) v dt2 t a = C10 to +85 c 0.8 1.6 2.2 v data retension voltage v ddr stop mode 1.3 v low-level output voltage m pd17215, 17216, 17217, 17218 68 item symbol conditions min. typ. max. unit i dd1 operating mode f x = 8 mhz 2 4 ma (high-speed mode) v dd = 5 v 10% i dd2 halt mode f x = 8 mhz 0.9 2.4 ma operating mode v dd = 5 v 10% 1.3 3.0 ma (high-speed mode) v dd = 3 v 10% 0.5 1.0 ma i dd3 f x = 4 mhz v dd = 5 v 10% 1.0 2.0 ma operating mode (ordinary mode) v dd = 3 v 10% 0.4 0.8 ma v dd = 2 to 2.2 v 0.2 0.4 ma v dd = 5 v 10% 0.8 1.8 ma i dd4 halt mode f x = 4 mhz v dd = 3 v 10% 0.3 0.6 ma v dd = 2 to 2.2 v 0.15 0.3 ma operating mode v dd = 3 v 10% 0.25 0.5 ma supply current i dd5 (high-speed mode) f x = 1 mhz v dd = 2 to 2.2 v 0.15 0.3 ma v dd = 3 v 10% 0.2 0.4 ma i dd6 halt mode f x = 1 mhz v dd = 2 to 2.2 v 0.1 0.2 ma v dd = 5 v 10% 1 30 m a stop mode i dd7 (t a = C40 to +85 c) v dd = 3 v 10% 1 20 m a v dd = 2 to 2.2 v 1 16 m a v dd = 5 v 10% 1 20 m a stop mode i dd8 (t a = C20 to +70 c) v dd = 3 v 10% 1 10 m a v dd = 2 to 2.2 v 1 8 m a v dd = 5 v 10% 1 5 m a stop mode i dd9 (t a = 25 c) v dd = 3 v 10% 1 5 m a v dd = 2 to 2.2 v 1 5 m a m pd17215, 17216, 17217, 17218 69 ac characteristics (v dd = 2.0 to 5.5 v, t a = C40 to +85 c) item symbol conditions min. typ. max. unit t cy1 v dd = 3.5 to 5.5 v 1.99 32.2 m s cpu clock cycle time* (instruction execution time) t cy2 v dd = 2.2 to 5.5 v 3.98 32.2 m s t cy3 7.96 32.2 m s int high/low level width t ioh, t iol v dd = 4.5 to 5.5 v 10 m s 50 m s reset low level width t rsl v dd = 4.5 to 5.5 v 10 m s 50 m s *: the cpu clock cycle time (instruction execution time) is determined by the oscillation frequency of the oscillator connected and sysck (rf: address 02h) of the register file. the figure on the right shows the cpu clock cycle time t cy vs. supply voltage v dd characteristics (refer to 4. clock generator circuit ). 40 32 10 9 8 7 6 5 4 3 2 0123456 t vs v dd cy cpu clock cycle time t [ s] cy m supply voltage v [v] dd 2.2 m pd17215, 17216, 17217, 17218 70 14. characteristic waveforms (reference value) i dd vs v dd (oscillation at 1 mhz) (t a = 25?) operating supply current i dd (ma) 3.0 2.0 1.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 supply voltage v dd (v) high-speed operation mode normal operation mode halt mode i dd vs v dd (oscillation at 4 mhz) (t a = 25?) operating supply current i dd (ma) 3.0 2.0 1.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 supply voltage v dd (v) high-speed operation mode normal operation mode halt mode i dd vs v dd (oscillation at 8 mhz) (t a = 25?) operating supply current i dd (ma) 3.0 2.0 1.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 5.5 normal operation mode halt mode high-speed operation mode supply voltage v dd (v) m pd17215, 17216, 17217, 17218 71 i dd vs f x (operation mode) (t a = 25?) operating supply current i dd (ma) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 01 4 8f x (mh z ) high-speed mode normal mode v dd = 3.0 v v dd = 5.0 v v dd = 3.0 v 1.2 1.0 0.8 0.6 0.4 0.2 0 01 4 8f x ( mh z ) halt current i dd (ma) i dd vs f x (halt mode) (t a = 25?) v dd = 5.0 v v dd = 5.0 v v dd = 3.0 v v dd = 2.0 v m pd17215, 17216, 17217, 17218 72 -40 -30 -20 -10 0 012345 v dd -v oh (v) (t a = 25?) i oh (rem) vs v dd -v oh high-level output current i oh (rem) (ma) -40 -30 -20 -10 0 012345 v dd -v oh (v) (t a = 25?) i oh (p0e) vs v dd -v oh high-level output current i oh (p0e) (ma) 40 30 20 10 0 012345 low-level output voltage v ol (v) (t a = 25?) i ol (rem/p0c/p0d) vs v ol low-level output current i ol (rem/p0c/p0d) (ma) 40 30 20 10 0 012345 (t a = 25?) i ol (p0e) vs v ol low-level output current i ol (p0e) (ma) v dd = 5.0 v v dd = 3.0 v v dd = 2.0 v v dd = 5.0 v v dd = 3.0 v v dd = 2.0 v v dd = 2.0 v v dd = 3.0 v v dd = 5.0 v v dd = 5.0 v v dd = 3.0 v v dd = 2.0 v low-level output voltage v ol (v) m pd17215, 17216, 17217, 17218 73 15. application circuit example 128 227 326 425 524 623 722 821 920 10 19 11 18 12 17 13 16 14 15 p0d 2 p0d 3 int p0e 0 p0e 1 p0e 2 p0e 3 rem p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 v dd x out x in gnd reset wdout 3 v 4 mhz pd17215ct/gt- pd17216ct/gt- m m pd17217ct/gt- pD17218ct/gt- m m remark: the reset pin can be connected to a pull-up resistor by the mask option. m pd17215, 17216, 17217, 17218 74 16. package drawings 28 pin plastic shrink dip (400 mil) item millimeters inches a b c f g h i j k 28.46 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 2.67 max. l 0.17 10.16 (t.p.) 5.08 max. 8.6 n 0.85 min. 1.121 max. 0.106 max. 0.033 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.400 (t.p.) 0.339 0.007 0.070 (t.p.) s28c-70-400b-1 a b i j g d 0.50?.10 0.020 m 0.25 0.010 +0.10 ?.05 r 0~15 0~15 +0.004 ?.005 +0.004 ?.003 notes each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. item "k" to center of leads when formed parallel. 1) 2) 28 15 114 m h c n f d m r k l m pd17215, 17216, 17217, 17218 75 28 pin plastic sop (375 mil) item millimeters inches a b c e f g h i j 18.07 max. 1.27 (t.p.) 2.9 max. 2.50 10.3?.3 0.78 max. 0.12 1.6 7.2 m 0.1?.1 n 0.712 max. 0.031 max. 0.004?.004 0.115 max. 0.098 0.406 0.283 0.063 0.005 0.050 (t.p.) p28gm-50-375b-3 p3 3 +7 a g note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.40 0.016 +0.10 ?.05 k 0.15 0.006 +0.10 ?.05 l 0.8?.2 0.031 0.15 ? +7 ? 0.006 +0.009 ?.008 +0.004 ?.002 +0.004 ?.003 +0.012 ?.013 p detail of lead end 114 28 15 m f e c dm b l k h i j n m pd17215, 17216, 17217, 17218 76 17. recommended soldering conditions for the m pd17215, 17216, 17217, and 17218, soldering must be performed under the following conditions. for details of recommended conditions for surface mounting, refer to information document "semiconductor device mounting technology manual" (c10535e). for other soldering methods, please consult with nec personnel. table 17-1 soldering conditions of surface mount tye m pd17215gt-xxx: 28-pin plastic sop (375 mil) m pd17216gt-xxx: 28-pin plastic sop (375 mil) m pd17217gt-xxx: 28-pin plastic sop (375 mil) m pD17218gt-xxx: 28-pin plastic sop (375 mil) soldering method soldering conditions symbol infrated reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), ir35-207-2 number of times: 2 max., days: 7 days* (after that, prebaking is necessary for 20 hours at 125 c) m pd17215, 17216, 17217, 17218 77 appendix a. differences among m pd17215, 17216, 17217, 17218 and m pd17p218 m pd17p218 is equipped with prom to which data can be written by the user instead of the internal mask rom (program memory) of the m pD17218. table a-1 shows the differences between the m pd17215, 17216, 17217, 17218 and m pd17p218. the differences among these five models are the program memory and mask option, and their cpu functions and internal hardware are identical. therefore, the m pd17p218 can be used to evaluate the program developed for the m pd17215, 17216, 17217, and 17218 system. note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the m pd17p218 are different from those of the m pd17215, 17216, 17217, and 17218. table a-1 differences among m pd17215, 17216, 17217, 17218 and m pd17p218 product name item m pd17p218 m pd17215 m pd17216 m pd17217 m pD17218 one-time prom mask rom program memory 16 k bytes (8192 16) 4 k bytes (2048 16) 8 k bytes (4096 16) 12 k bytes (6144 16) 16 k bytes (8192 16) (0000h-1fffh) (0000h-07ffh) (0000h-0fffh) (0000h-17ffh) (0000h-1fffh) data memory 223 4 bits 111 4 bits 223 4 bits pull-up resistor of reset pin provided any (mask option) low-voltage detector circuit * provided any (mask option) v pp pin, operation mode select pin provided not provided 2 m s (8 mhz ceramic oscillator: in high-speed mode) instruction execution time 4 m s (4 mhz ceramic oscillator: in high-speed mode) 16 m s (1 mhz ceramic oscillator: in high-speed mode) operation when p0c, p0d are retain output level immediately before standby mode standby supply voltage v dd = 2.2 to 5.5 v (at f x = 4 mhz, in high-speed mode) package 28-pin plastic sop (375 mil) 28-pin plastic shrink dip (400 mil) *: although the circuit configuration is identical, its electrical characterisitcs differ depending on the product. m pd17215, 17216, 17217, 17218 78 ? ? appendix b. functional comparison of m pd17215 subseries related products product name m pd17201a m pd17207 m pd17202a m pd17215 m pd17216 m pd17217 m pD17218 item rom capacity (bit) 3072 16 4096 16 2048 16 4096 16 6144 16 8192 16 ram capacity (bit) 336 4 112 4 111 4 223 4 lcd controller/driver 136 segments max. 96 segments not provided max. infrared remote controller led output is led output carrier generator (rem) high-actives is low- internal (no led output) actives i/o ports 19 lines 16 lines 20 lines external interrupt (int) 1 line 1 line (rising-edge, falling-edge, detection) (rising-edge detection) analog input 4-channels (8-bit a/d) not provided timer 2-channels 8-bit timer 2-channels 8-bit timer watch timer basic interval timer watchdog timer internal (wdout output) low-voltage detector not provided internal (wdout output) circuit* serial interface 1-channel not provided stack 5 levels (3 levels for multiplexed interrupt) 2 m s (8 mhz ceramic oscillator: main 4 m s in high-speed mode) instruction system (4 mhz: with ceramic or crystal 4 m s (4 mhz ceramic oscillator: execution clock oscillator) in high-speed mode) time 16 m s (1 mhz ceramic oscillator: in high-speed mode) subsystem 488 ms (32.768 khz: with crystall not provided clock oscillator) supply voltage v dd = 2.2 to 5.5 v (v dd = 2.0 to 5.5 v) v dd = 2.2 to 5.5 v (with subsystem clock) standby function stop, halt package 80-pin plastic qfp 64-pin 28-pin plastic sop plastic qfp 28-pin plastic shrink dip one-time prom products m pd17p207 m pd17p202a m pd17p218 *: note that although all the prodcts have the same circuit construction, the electrical specifications differ dependant on each product. m pd17215, 17216, 17217, 17218 79 in-circuit emulator ie-17k, ie-17k-et * 1 , emu-17k * 2 appendix c. development tools to develop the programs for the m pd17215 subseries, the following development tools are available: hardware name remarks ie-17k, ie-17k-et, and emu-17k are the in-circuit emulators used in common with the 17k series microcomputer. ie-17k and ie-17k-et are connected to a pc-9800 series or ibm pc/at tm as the host machine with rs-232c. emu-17k is inserted into the expansion slot of a pc-9800 series. by using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. a higher level debugging environment can be provided by using man-machine interface simplehost tm . emu-17k also has a function by which you can check the contents of data memory real-time. se board this is an se board for m pd17215 subseries. it can be used alone to evaluate a system (se-17215) or in combination with an in-circuit emulator for debugging. emulation probe ep-17k28ct is an emulation probe for 17k series 28-pin shrink dip (400mil). (ep-17k28ct) emulation probe ep-17k28gt is an emulation probe for 17k series 28-pin sop (375 mil). when used with (ep-17k28gt) ev-9500gt-28 note 3 , it connects an se board to the target system. conversion adapter ev-9500gt-28 is a conversion adapter for 28-pin sop (375 mil) and is used to connect (ev-9500gt-28 * 3 ) ep-17k28gt to the target system. prom programmer af-9703, af-9704, af-9705, and af-9706 are prom programmers corresponding to m pd17p218. (af-9703 * 4 , af-9704 * 4 , by connecting program adapter af-9808j or af-9808h to this prom programmer, af-9705 * 4 , af-9706 * 4 ) m pd17p218 can be programmed. program adapter af-9808j and af-9808h are adapters that is used to program m pd17p218ct and (af-9808j * 4 , m pd17p218gt respectively, and is used in combination with af-9703, af-9704, af-9705, af-9808h * 4 ) or af-9706. *1: low-cost model: external power supply type 2: this is a product from i.c corp. for details, consult i.c corp. (tel: tokyo 03-3447-3793). 3: two ev-9500gt-28s are supplied with the ep-17k28gt. five ev-9500gt-28s are optionally available as a set. 4: these are products from ando electric co., ltd. for details, consult ando electric co., ltd. (tel: tokyo 03- 3733-1163). m pd17215, 17216, 17217, 17218 80 software outline as17k is an assembler common to the 17k series products. when developing the program of the m pd17215 subseries, as17k is used in combination with a device file (as17215, as17216, as17217, or as17218). as17215, as17216, as17217, and as17218 are device files for m pd17215, 17216, 17217, and 17218 respectirely, and are used in combination with an assembler for the 17k series (as17k). simplehost is a software package that enables man- machine interface on the windows tm when a program is developed by using an in-circuit emulator and a personal computer. order code m s5a10as17k m s5a13as17k m s7b10as17k m s7b13as17k m s5a10as17215 * m s5a10as17215 * m s5a10as17215 * m s5a10as17215 * m s5a10ie17k m s5a13ie17k m s7b10ie17k m s7b13ie17k supply 5" 2hd 3.5" 2hd 5" 2hc 3.5" 2hc 5" 2hd 3.5" 2hd 5" 2hc 3.5" 2hc 5" 2hd 3.5" 2hd 5" 2hc 3.5" 2hc os media ms-dos tm pc dos tm ms-dos pc dos ms-dos windows pc dos host machine pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at name 17k series assembler (as17k) device file as17215 as17216 as17217 as17218 support software ( simple- host ) *: m s as17215 includes as17215, as17216, as17217, and as17218. remark: the corresponding os versions are as follows: *: ver. 5.00/5.00a of ms-dos and ver. 5.0 of pc dos have a task swap function, but this function cannot be used with this software. os version ms-dos ver. 3.30 to ver. 5.00a * pc dos ver. 3.1 to ver. 5.0 * windows ver. 3.0 to ver. 3.1 m pd17215, 17216, 17217, 17218 81 [memo] m pd17215, 17216, 17217, 17218 82 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. m pd17215, 17216, 17217, 17218 83 m pd17215, 17216, 17217, 17218 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 simplehost is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. |
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